Transmitter for transmitting digital data over a transmission line

ABSTRACT

The invention relates to a transmitter for transmission of digital data via a transmission line ( 10 ), comprising a current-driving digital/analogue converter ( 1 ) which is arranged at the input of the transmitter; a current-operated form filter ( 2 ) for forming the current pulses which are supplied from the digital/analogue converter; a line driver ( 5 ) which carries out current/voltage conversion; and a circuit for offset compensation ( 6 ), which is arranged in a feedback path ( 11 ). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.

[0001] The invention relates to a transmitter for transmission ofdigital data via a transmission line, which is used in particular intelecommunications systems.

[0002] In order to ensure error-free data transmission, the pulse format the output of a transmitter (Line Interface Unit) must comply withspecific specifications (see CCITT G.703 Physical/ElectricalCharacteristics of Hierarchical Digital Interfaces). Appropriatestandard pulse masks, which the transmitters have to comply with, arespecified as a function of the data rate and of the chosen Standard.

[0003] Transmitters which have been developed to date have been able tosatisfy the specified Standards satisfactorily only when sufficientoperating voltage was available. The concept of such known lineinterface units is predominantly based on voltage-processing principlesin the signal path of the transmitters, which may have resulted incertain fluctuation in the operating points in the correspondingcircuits, and entailing restricted-quality operation of the overalltransmitter. Furthermore, these principles are only inadequatelysuitable for modern deep submicron CMOS processes and the withstandvoltage, which is restricted as a consequence of this, of regular MOStransistors.

[0004] Furthermore, the circuits of known transmitters have relativelyhigh-value mode impedances, which in turn result in severe thermal noiseand thus have a limited signal-to-noise ratio. Apart from this, theknown transmitters were sensitive to offset voltages, which cause anundesirable direct current via the load at the output. In particular,the prior saturation of a downstream transformer can lead to additionalundesirable distortion of the signal.

[0005] A range of publications exists in which voltage-processingtransmitters are described. These include, for example:

[0006] H. Herrman and R. Koch: “A 1.544 Mb/s CMOS Line Driver for 22.8 ΩLoad”, IEEE Journal of Solid-State Circuits, June 1990, Pages 760 etc.,

[0007] Haideh Khorramabadi: “Highly Efficient CMOS Line Drive with 80 dBLinearity for ISDN U-Interface Applications”, IEEE Journal ofSolid-State Circuits, December 1992, Pages 1723 etc., and

[0008] M. Moyal, M. Gröbel and Th. Blon: “A 25 kft, 768 kb/s CMOS AnalogFront End for Multible-Bit-Rate DSL Transceiver”, IEEE Journal ofSolid-State Circuits, December 1999, Pages 1961 etc., and the referencescited in these documents. The known solutions, however, are subject toall of the disadvantages that have been mentioned above.

[0009] The object of the present invention is thus to provide atransmitter for transmission of digital data, which allows thegeneration of pulses of considerably higher quality and accuracy, andwhich avoids the disadvantages of voltage-processing principles forsignal generation.

[0010] This object is achieved by the features specified in patent claim1. Further refinements of the invention are the subject matter ofdependent claims.

[0011] The major idea of the invention is for the internal signalprocessing in the transmitter to be carried out on a current basis; thistype of signal processing is referred to in the specialist literature asthe current-mode approach. Only the interface to the “outside world” ispreferably provided by transistors that are more resistant to voltage inorder to drive the signals to the load or to the cable.

[0012] Furthermore, the invention avoids the need to provide feedbackloops in the signal path, for example in the filter and in the currentamplifiers, of the transmitter.

[0013] Feedback loops can have a negative influence on the stability ofthe transmitter.

[0014] The transmitter according to the invention for transmission ofdigital data via a transmission line thus comprises at least thefollowing current-operated circuits without feedback loops, namely:

[0015] a current-driving digital/analogue converter which forms theinput of the transmitter;

[0016] a current-operated form filter for forming (smoothing) thequantized current pulses which are supplied from the digital/analogueconverter;

[0017] a line driver which carries out current/voltage conversion andforms the output of the transmitter; and

[0018] a circuit for offset compensation.

[0019] Furthermore, a level shifter can be provided for conversion of alower supply voltage to a higher supply voltage;

[0020] A current-operated amplifier or buffer is preferably arranged atthe output of the digital/analogue converter, for isolation of theconverted output.

[0021] The current-operated amplifier initially divides the amplitudesof the pulses which are supplied from the digital/analogue converter bya specific factor N. The expression amplifier is in the following textalso intended to include amplifiers which operate with a step-downratio, that is to say which divide the current.

[0022] The current-operated amplifier essentially forms acurrent-controlled current source and, according to one preferredembodiment, comprises a current mirror.

[0023] According to one refinement of the invention, thecurrent-operated form filter comprises a current-operated low-passfilter for forming the data pulses, and which preferably likewise has acurrent mirror. The current-operated form filter produces desiredpre-emphasis, depending on the chosen Standard and/or application, ofthe transmission pulses which are emitted at the transmitter output, andis at the same time used as a form filter for the DA current pulses.

[0024] According to one preferred refinement of the invention, thecut-off frequency of the low-pass filter is switchable.

[0025] A current-controlled current amplifier is preferably provideddownstream from the form filter in the signal path of the transmitter,and may likewise be formed from a current mirror circuit.

[0026] According to one preferred refinement of the invention, acurrent-controlled level shifter is also provided in the signal path ofthe transmitter and allows the part of the circuit located upstream ofit to be operated with a lower supply voltage. The level shifter ispreferably likewise formed with a current mirror.

[0027] According to one preferred refinement of the invention, thecurrent mirrors which are used in the transmitter are equipped withvoltage regulation, which essentially stabilizes the node potential atthe input and/or at the output of the current mirror. The voltage levelat this node is thus virtually constant, and additional distortioncaused by a shift in the operating point and/or charge-shifting effectsdue to parasitic capacitances is reduced. The voltage regulation thusresults in the circuit always being at the optimum operating point.

[0028] The offset-compensation circuit which is arranged in a feedbackpath is preferably formed by means of transconductance stages. Theoffset compensation should have a low-pass filter characteristic inorder that the pulse that is produced at the output may comply with theStandards. In the forward direction, the low-pass filter with its polepoint acts as a high-pass filter with a zero point in the overalltransfer function of the transmitter. During design, care must be takento ensure that the effective zero point in the forward direction islower than the smallest spectral components of the transmission pulse.

[0029] The transmitter preferably uses differential path technology.

[0030] The invention will be explained in more detail in the followingtext using the figures, by way of example, in which:

[0031]FIG. 1: shows an exemplary embodiment of a transmitter which isbased on current processing and uses differential path technology;

[0032]FIG. 2 shows a current amplifier using differential pathtechnology, according to one refinement of the invention;

[0033]FIG. 3 shows one embodiment of a current filter;

[0034]FIG. 4 shows a level shifter, formed from current mirrors,according to one embodiment of the invention;

[0035]FIG. 5 shows a first exemplary embodiment of a voltage regulatorfor a current mirror;

[0036]FIG. 6 shows a further exemplary embodiment of a voltage regulatorfor a current mirror;

[0037]FIG. 7 shows a first exemplary embodiment of a feedback circuitfor offset compensation;

[0038]FIG. 8 shows a simple equivalent circuit for calculation of thetransmission characteristics in the frequency domain for the transmittershown in FIG. 1.

[0039]FIG. 1 shows a schematic block diagram of a transmitter comprisinga digital/analogue converter 1, a form filter 2, a current amplifier 3,a level shifter 4, and a line driver 5. The elements 1-5 form the signalpath of the transmitter.

[0040] A circuit for offset compensation 6, with a low-pass filtercharacteristic, is provided in the feedback path 12 of the transmitter.

[0041] A reference current production device 7 provides a referencecurrent, which is supplied to all the units 1-6. All the pulse currentsas well as the currents for setting the operating point are thus derivedfrom the reference current, thus avoiding undesirable offsets resultingfrom lack of synchronization. It is also feasible for the variouscomponents of the transmitter to be supplied with intrinsicallyindependent currents. This must be decided on the basis of therequirements of bandwidths, linearity, etc.

[0042] The reference current can additionally be adjusted in order toincrease the accuracy of the pulse amplitude of the transmission pulses,and thus to guarantee compliance of specific pulse masks with variousStandards.

[0043] The digital/analogue converter 1 forms the input of thetransmitter, and is in the form of a current-driving digital/analogueconverter. The digital data which is supplied at the input is decoded ina decoder 13, in order in this way to switch weighted current sources14. Internal regulation (not shown) ensures matching of the PNOS andNMOS current mirrors within the digital/analogue converter.

[0044] Differential current pulses are produced at the outputs 15 of theD/A converter (comprising a DACP and a DACN), and are supplied to acurrent-controlled form filter 2.

[0045] The form filter 2 comprises a current divider 8 and a low-passfilter 9, which provides desired pre-emphasis of the transmission pulseswhich are emitted at the output of the transmitter, and is at the sametime used as a form filter for the DA current pulses. The currentamplifier is in this case in the form of a divider 8, which divides theamplitude of the arriving current pulses by a specific factor N. In thiscase, this is carried out only by way of example in order to reduce thepower consumption or the surface area required for the downstreamlow-pass filter. It is also feasible for the signal current not beattenuated but to be amplified. The amplifier or divider stage 8 shouldin any case be designed to provide decoupling between the DA converter 1and the filter 9.

[0046] The transmission characteristics of the current amplifier shownin FIG. 2 in the frequency domain is given, in a simplified form, by thefollowing equation: $\begin{matrix}{{A_{iv}(s)} = {\frac{i_{out}(s)}{i_{in}(s)} \equiv {\frac{{gm}_{N1}}{{gm}_{N2}}*\left( \frac{1}{1 + {s*\frac{C_{N1}}{{gm}_{N1}}}} \right)} \equiv {\frac{{gm}_{N1}}{{gm}_{N2}}*\left( \frac{1}{1 + \frac{s}{\omega_{iv}}} \right)}}} & \lbrack 1.1\rbrack\end{matrix}$

[0047] where

[0048] gmN1 is the gradient of the transistor N1,

[0049] gmN2 is the gradient of the transistor N2,

[0050] CN1 is the sum of the capacitances at the gate of the transistorN1, and

[0051] ω is the pole frequency of the parasitic pole of the mirror.

[0052] The subsequent low-pass filter 9 provides the desired signalforming and pre-emphasis, and preferably operates on the principle ofGmC filtering. The transmission characteristic of the form-filter shownin FIG. 3 in the frequency domain is given by the following equation,$\begin{matrix}\begin{matrix}{{A_{ltp}(s)} = {\frac{i_{out}(s)}{i_{in}(s)} \equiv {\frac{R1}{R2}*\left( \frac{1 + \frac{1}{{gm}_{N1}*{R1}}}{1 + \frac{1}{{gm}_{N2}*{R2}}} \right)\left( \frac{1}{1 + \frac{s*C_{N1}}{\left( {{gm}_{N1} + {R1}} \right)}} \right)}}} \\{\cong {\frac{R1}{R2}*\left( \frac{1 + \frac{1}{{gm}_{N1}*{R1}}}{1 + \frac{1}{{gm}_{N2}*{R2}}} \right)\left( \frac{1}{1 + \frac{s}{\omega_{ip}}} \right)}}\end{matrix} & \lbrack 1.2\rbrack\end{matrix}$

[0053] where

[0054] gmN1 is the gradient of the transistor N1,

[0055] gmN2 is the gradient of the transistor N2,

[0056] R1 is the degeneration resistance of the transistor N1,

[0057] R2 is the degeneration resistance of the transistor N2,

[0058] CN1 is the sum of the capacitances of the gate of the transistorN1, and

[0059] ω is the pole frequency of the dominant pole of the mirror.

[0060] The pre-emphasized current pulses are amplified by a specificfactor N in the current amplifier 3. The transfer function within thefrequency domain is given by equation 1.1. The implementation of thecurrent amplifier corresponds to FIG. 2. The factor N is given by:$\begin{matrix}{N = {\frac{i_{out}}{i_{in}} \cong \frac{{gm}_{N1}}{{gm}_{N2}}}} & \lbrack 1.3\rbrack\end{matrix}$

[0061] where

[0062] gmN1 is the gradient of the transistor N1,

[0063] gmN2 is the gradient of the transistor N2.

[0064] A level shifter 4 is optionally connected to the output of thecurrent amplifier 3, transforms the supply voltage from a low supplyvoltage VDD1 to a higher supply voltage VDD2 and allows the circuit partwhich is located upstream of it to be operated with a lower supplyvoltage VDD1. This has the major advantage that it is possible to usetransistors with a thinner gate oxide based on modern sub-microntechnologies for the signal path. This is in turn evident in a higherspeed and in a lower current consumption.

[0065] The line driver 6 comprises an operational amplifier (OPV) withfeedback resistors Rfb, by means of which the current pulses areconverted to voltage pulses, as required for transmission. Thisconfiguration is generally referred to as shunt-shunt feedback. Thetransfer function for the frequency domain is thus given by:$\begin{matrix}\begin{matrix}{{A_{ir}(s)} = {R_{fb}*\frac{1}{1 + {T_{loop}(s)}}}} \\{= {R_{fb}*{\frac{1}{1 + {\frac{R_{fb}*R_{L}}{R_{fb} + R_{L} + {R_{OPV}*R_{fb}} + {R_{OPV}*R_{L}}}*\quad {A_{OPA}(s)}*\frac{R_{IOPA}}{R_{IOPA} + R_{fb}}}}\lbrack\Omega\rbrack}}}\end{matrix} & \lbrack 1.4\rbrack\end{matrix}$

[0066] where

[0067] Tloop(s) is the open loop gain,

[0068] RL is the load resistance of the output of the current/voltageconverter,

[0069] ROOPV is the output resistance of the OPV,

[0070] RIOPA is the input resistance of the OPV, and

[0071] AOPA(s) is the open gain in the frequency domain of the OPV.

[0072] The unit for the transfer function is Ohm [!].

[0073] The transmission line 10 is terminated in a known manner by aline resistance RL.

[0074] The offset compensation circuit 6 compensates for any DC offsetbetween the outputs of the line drivers XL1 and XL2. This circuit 6 ispreferably formed from transconductance stages, and is fed back to theoutput 15 of the digital/analogue converter. As a guideline for thedesign of the offset compensation 6, the pole frequency should be belowthe lowest spectral component of the transmission pulses, and shouldhave a corresponding low-pass filter characteristic.

[0075] The transmission characteristic of the offset compensationcircuit shown in FIG. 7 in the frequency domain is given, in simplifiedform, by: $\begin{matrix}{{A_{fb}(s)} = {\frac{i_{rfb}(s)}{v_{out}(s)} \equiv {{Gm1}*R_{oGm1}*{Gm2}*\left( \frac{1}{1 + {s*\frac{C_{fb}}{{Gm1} + R_{oGm1}}}} \right)} \cong {G_{ofb}*{\left( \frac{1}{1 + \frac{s}{\omega_{fb}}} \right)\left\lbrack \frac{1}{\Omega} \right\rbrack}}}} & \lbrack 1.5\rbrack\end{matrix}$

[0076] where

[0077] Gm1 is the gradient of the transconductance stage 1,

[0078] Gm2 is the gradient of the transconductance stage 2,

[0079] ROGm1 is the output resistance of the transconductance stage Gm1,

[0080] Cfb is the sum of the capacitors of the output of thetransconductance Gm1,

[0081] ωfb is the pole frequency of the dominant pole of the offsetcompensation, and

[0082] G0fb is the total transconductance of the feedback.

[0083]FIG. 2 shows a simplified structure of a current amplifier 8 usingdifferential path technology with mid-voltage regulation (Common ModeFeedback). The differential inputs of the current amplifier or dividerare denoted INP and INN (P: Positive, N: Negative), and thecorresponding outputs are denoted OUTP and OUTN.

[0084] Each differential path comprises a current mirror 20 with mirrortransistors N1, N2 and N1′, N2′. Appropriate choice of the mirror ratioN of the current mirror transistors N1, N2 and N1′ and N2′ makes itpossible to either amplify the input current by the factor N (N>1) or todivide it by the factor N (N≦1). If N=1, this results in a currentbuffer. The transfer function in equation 1.1 applies in the frequencydomain to the current divider 8 shown in FIG. 1. The staging ratio isgiven by: $\begin{matrix}{N = {\frac{i_{out}}{i_{in}} \cong \frac{{gm}_{N1}}{{gm}_{N2}}}} & \lbrack 1.6\rbrack\end{matrix}$

[0085] where

[0086] gmN1 is the gradient of the transistor N1, and

[0087] gmN2 is the gradient of the transistor N2.

[0088] In order to increase the output resistance of the current mirror20, it is also possible to use an additional cascode transistor or aregulated cascode (not shown). The expression “current mirror” in thisdescription is intended to mean all possible versions. The descriptionof the figures is restricted to the simplest form of current mirrorsonly in order to explain the operation.

[0089] Mirror transistors N1, N2 and N1′ and N2′ are each connected to acurrent source 22, which supplies a current that is derived from thereference current I_(Ref).

[0090] The inputs INP, INN of the current amplifier are clamped at apredetermined potential by DC voltage regulation 21. The DC voltageregulation keeps the operating point of the current mirror 20 in a rangewhich is as ideal as possible. The DC voltage regulation comprises atransistor P1 or P1′, which is connected between the respectivedifferential input INP, INN and the respective mirror transistor N1,N1′.

[0091]FIG. 3 shows a current filter which is physically virtuallyidentical to the current amplifier 8 shown in FIG. 2. The current orform filter likewise comprises current mirrors 20 with mirrortransistors N1, N2 and N1′, N2′. The transistors P1 and P1′ regulate theinput voltage at the nodes INP, INN.

[0092] Degeneration resistors R1, R2 and R1′, R2′, respectively, whichincrease the linear drive range, are connected to the source connectionsof the respective transistors N1, N2 and N1′, N2′. The filtered responseresults from the sum of the degeneration resistance R1 (R1) and thereciprocal of the conductance of the transistor N1 (N1′) in parallelwith the capacitance C (C′) which is connected to ground at the mirrorpoint of the transistors N1, N2 and N1′, N2′ respectively. The productof the resistance value and capacitance is proportional to the polefrequency of the filter.

[0093] It should be noted that the transistors N2 and N2′ form aparasitic pole by the diffusion capacitance at the drain connection, andthis must be taken into account in the transmission characteristic.

[0094]FIG. 4 shows a level shifter 4, which is likewise formed fromcurrent mirrors 20. The level shifter 4 is used for matching thedifferent supply voltages VDD1, VDD2 to the components in the signalpath. The transistors N1, N1′ and N2, N2′ respectively form a currentmirror, in the same way as the transistors P2, P2′ and P3, P3′. Acascode transistor N3 (N3′) is provided at the drain connection of thetransistor N2, and must be suitable for a higher operating voltage.

[0095] The potential of the input INP, INN of this stage, and hence alsothe potential of the output of the previous stage, are stabilized by DCvoltage regulation 21.

[0096]FIG. 5 shows one possible implementation of DC voltage regulation21 with an operational amplifier 21, whose inverted input is connectedto the signal input of the stage, and whose non-inverted input isconnected to a reference voltage. The output of the operation amplifier23 is connected to the gate connection of the transistor P1.

[0097]FIG. 6 shows another implementation of the voltage regulation 21.The voltage regulation 21 comprises a current mirror 23 which is formedfrom the transistors P4 and P5. A resistor R_(CM) is provided at thesource connection of the transistor P5. A current source I_(O) isconnected to the source connection of the transistor P4. The drainconnection of the transistor P5 is connected to a reference currentsource I_(REF). The transistor P4 is connected to a current mirror 20 inone of the stages 2-4 described above. This circuitry results in aconstant potential U₀ at the input. The voltage regulation can also beprovided at the output of one of the stages 2-4.

[0098]FIG. 7 illustrates one possible implementation of the feedbackcircuit 6 for offset compensation. The feedback comprises a firsttransconductance stage Gm1, a second transconductance stage Gm2 and acapacitance Cfb. The input nodes INP and INN are connected to theoutputs XL1 and XL2 in the transmitter shown in FIG. 1. The outputs OUTPand OUTN are connected to the connections DACN and DACP. The capacitanceis connected between the outputs of the first transconductance Gm1 andthe inputs of the second transconductance Gm2. The dominant pole of thearrangement is formed from the quotient of the gradient of the firsttransconductance stage Gm1 and of the capacitance Cfb.

[0099]FIG. 8 shows a simplified illustration of the transmission chainin the transmitter shown in FIG. 1. The transfer function from theoutput of the digital/analogue converter to the transmitter output iscalculated taking into account the equations mentioned above as follows:$\begin{matrix}{{{G_{TR}(s)} = {\frac{V_{out}(s)}{i_{o}(s)} = \frac{H_{fw}(s)}{1 + {{A_{fb}(s)}*{H_{fw}(s)}}}}}{and}{{H_{fw}(s)} = {{{A_{iv1}(s)}*{A_{irp}(s)}*{A_{iv2}(s)}*{A_{tr}(s)}} = {\left( {N*\frac{1}{1 + \frac{s}{\omega_{iv1}}}} \right)*\frac{R1}{R2}\left( \frac{1 + \frac{1}{{gm}_{N1}*{R1}}}{1 + \frac{1}{{gm}_{N2}*{R2}}} \right){\quad{\left( \frac{1}{1 + \frac{s}{\omega_{tp}}} \right)*}\quad}{\quad{\left( {M*\frac{1}{1 + \frac{s}{\omega_{iv2}}}} \right)*\left( {R_{fb}*\frac{1}{1 + {T_{loop}(s)}}} \right)}}}}}} & \lbrack 1.7\rbrack\end{matrix}$

[0100] where

[0101] GTR(s) is the transfer function in the frequency domain of theentire transmitter,

[0102] Hfw(s) is the forward gain of the arrangement,

[0103] Afb(s) is the transfer function in the frequency domain of thefeedback for offset compensation,

[0104] ωiv1 is the pole frequency of the parasitic pole of the amplifierstage 8 shown in FIG. 1,

[0105] ωiv2 is the pole frequency of the parasitic pole of the amplifierstage 3 shown in FIG. 1, and

[0106] Atr(s) is the transfer function in the frequency domain of theshunt-shunt feedback 5 shown in FIG. 1.

[0107] The following relationship can be quoted, in simplified form, asthe reference point for the harmonic distortion that is to be expectedinside the transmitter: $\begin{matrix}{{{HD}_{2\quad} \cong {\frac{1}{8}*\frac{I_{AC}}{I_{DC}}*\frac{\omega}{{gm}_{Nx}/C_{\ln \quad {Nx}}}}} = {\frac{1}{8}*\frac{I_{AC}}{I_{DC}}*\frac{\omega}{\omega_{DP}}}} & \lbrack 1.8\rbrack\end{matrix}$

[0108] where

[0109] HD2 is the second harmonic of the transmitter,

[0110] IAC is the amplitude of the signal current,

[0111] IDC is the supply current in the transistor,

[0112] ω is the instantaneous angular frequency of the signal current,

[0113] ωDP is the dominant pole in the forward signal path of thetransmitter,

[0114] gmNx is the gradient of the transistor at which the dominant poleis produced, and

[0115] CinNx is the total capacitance of the input or output of thetransistor at which the dominant pole is produced.

[0116] One major advantage of the invention can be seen from theequation 1.8. The second harmonic distortion HD2 can be chosen optimallyby suitable choice of the bandwidth, by reduction of the parasitic modecapacitances, and by a suitable ratio of the signal current to thesupply current for operating point adjustment.

[0117] The individual components of the transmitter can be designed andimplemented independently of the details of the practicalimplementation, with the aid of the stated equations, and, even if theinternal supply voltage is low, they represent a stable and reliableimplementation for pulse generation and transmission of data.

[0118] List of Reference Symbols

[0119]1 Digital/analogue converter

[0120]2 Form filter

[0121]3 Current amplifier

[0122]4 Level shifter

[0123]5 Line driver

[0124]6 Offset compensation

[0125]7 Reference current production

[0126]8 Amplifier

[0127]9 Low pass filter

[0128]10 Transmission line

[0129]11 Signal path

[0130]12 Feedback path

[0131]13 Decoder

[0132]14 Current sources

[0133]15 Output

[0134]20 Current mirror

[0135]21 Voltage regulator

[0136]22 Current sources

[0137]23 Operation amplifier

[0138] INN, INP Differential inputs

[0139] OUTN, OUTP Differential outputs

[0140] N1, N1′ Mirror transistors

[0141] N2, N2′ Mirror transistors

[0142] P2, P2′ Mirror transistors

[0143] P3, P3′ Mirror transistors

[0144] R1, R1′ Degeneration resistors

[0145] R2, R2′ Degeneration resistors

[0146] P1, P1′ Transistor

[0147] N3, N3′ Cascode transistor

[0148] VDD1 Low operating voltage

[0149] VDD2 High operating voltage

[0150] RL Line resistance

1. A transmitter for transmission of digital data via a transmissionline (10), comprising a current-driving digital/analogue converter (1)which is arranged at the input of the transmitter; a current-operatedform filter (2) for forming the current pulses which are supplied fromthe digital/analogue converter; a line driver (5) which carries outcurrent/voltage conversion; and a circuit for offset compensation (6),which is arranged in a feedback path (11) of the transmitter.
 2. Thetransmitter as claimed in claim 1, characterized in that acurrent-operated amplifier (8) is provided at the output of thedigital/analogue converter (1) in order to isolate the converter outputfrom the downstream circuits.
 3. The transmitter as claimed in claim 2,characterized in that the current-operated amplifier (8) divides thecurrent that is supplied from the digital/analogue converter (1) by afactor of N.
 4. The transmitter as claimed in claim 2 or 3,characterized in that the amplifier (8) has a current mirror (20). 5.The transmitter as claimed in one of the preceding claims, characterizedin that the form filter (2) has a current-operated low-pass filter (9)which is connected downstream from the amplifier (8).
 6. The transmitteras claimed in claim 5, characterized in that the low-pass filter (9) hasa current mirror (20).
 7. The transmitter as claimed in one of thepreceding claims, characterized in that the form filter (2) producesdesired pre-emphasis of the transmission pulses which are transmitted atthe output of the transmitter.
 8. The transmitter as claimed in one ofclaims 5 to 7, characterized in that the cut-off frequency of thelow-pass filter (9), and thus its pre-emphasis, are switchable.
 9. Thetransmitter as claimed in claim 4 or 5, characterized in that thecurrent mirror (20) has voltage regulation (21) which essentiallystabilizes the voltage at the signal input (IN) and/or output (OUT). 10.The transmitter as claimed in one of the preceding claims, characterizedin that a current-controlled current amplifier (3) is provided in thesignal path (11) of the transmitter.
 11. The transmitter as claimed inone of the preceding claims, characterized in that a current-controlledlevel shifter (4) is arranged in the signal part (11) of thetransmitter, and converts a lower supply voltage (VDD1) to a highersupply voltage (VDD2).
 12. The transmitter as claimed in claim 10,characterized in that the current amplifier (3) has a current mirror(20).
 13. The transmitter as claimed in claim 11, characterized in thatthe level shifter (4) has a current mirror (20).
 14. The transmitter asclaimed in one of the preceding claims, characterized in that thecircuit for offset compensation (6) is formed from transconductancestages.
 15. The transmitter as claimed in one of the preceding claims,characterized in that the circuit for offset compensation (6) has alow-pass filter characteristic.
 16. The transmitter as claimed in one ofthe preceding claims, characterized in that the transmitter usesdifferential path technology.